使用Allegro电流传感器IC（ACS724和ACS780）时最小化共模场干扰的技术
使用Allegro电流传感器IC（ACS724和ACS780）时最小化共模场干扰的技术
By Evan Shorman,
Allegro MicroSystems, LLC
介绍
Allegro MicroSystems current sensor ICs can be divided into three main groups: sensors that need an external magnetic core, sensors that have a core built into the package, and sensors that have an integrated current-carrying loop but no core. Among the latter group are sensors that have common-mode field rejection (CMR) capabilities. This application note will discuss the mechanism of CMR and focus on how to best use this mechanism through optimized circuit board design and layout.
Background
在使用集成载流回路的集成电路中，回路设计用于产生可由集成电路测量的磁场。磁场利用霍尔效应转化为电压。霍尔电压与电流的大小和方向成正比。图1是特定电流传感器IC引线框架如何产生磁场的示例。在图中，箭头显示了通过引线框架的电流，彩色图描述了100 A直流电流流过传感器时产生的磁场。为了清楚起见，图中去掉了电流的来源。
There are many advantages to using an IC with an integrated current-carrying loop: no need for a core, virtually no magnetic hysteresis, low power dissipation, and high accuracy over temperature. However, because the core is no longer present, the sensor is susceptible to stray magnetic fields generated by magnets or currents flowing in wires around the sensor IC. To combat the presence of stray magnetic fields, many of Allegro’s current sensors have a dual-Hall common-mode rejection scheme. The Hall plates are placed in such a way that the field sensed on each Hall plate is of opposite polarity when current is flowing through the IC’s integrated conductor or loop. In Figure 1, two Hall plate locations are denoted as H1 and H2. It can be observed from the figure that these two areas have magnetic fields that are opposite in direction.
This is the basic principle of the CMR techniques used: if the signals from the two Hall plates are subtracted, then the signals caused by the current in the integrated loop can be summed, and the common-mode (single polarity) signals coming from any stray magnetic fields incident on the IC can be rejected. For a simple example, assume that the magnetic field on each Hall plate, ±B, is equal but opposite; then:
H1 – H2 ∝ B1 – B2
B–B2=B–（–B）
B – (–B) = 2 × B
因此，
H1–H2∞2×B
If it is assumed that there is an equal stray magnetic field, Bext，然后：
H1 – H2 ∝ B1 – B2
B1–B2=（B+B）ext) – (–B + Bext)
(B + Bext) – (–B + Bext) = 2 × B + Bext– Bext
2×B+Bext– Bext= 2 × B
因此，
H1–H2∞2×B
In the application note,Common Mode Field Rejection in Coreless Hall-Effect Current Sensor ICs, the theory and governing equations of the CMR technique are covered in more detail. The main technique covered in this application note will be how to design and layout the current-carrying traces to these current sensor ICs. In addition, the application note provides guidance on minimizing other sources of stray fields.
Field from Nearby Current Path
To best use the CMR capabilities of these devices, the circuit board containing the ICs should be designed to make the external magnetic fields on both Hall plates equal. This helps to minimize error due to external fields generated by the current-carrying PCB traces themselves. There are three main parameters for each current-carrying trace that determine the error that it will induce on an IC:distance从集成电路,宽度载流导体，以及角between it and the IC. Figure 2 shows an example of a current-carrying conductor routed near an IC. The distance between the device and the conductor,d, is the distance from the device center to the center of the conductor. The width of the current path isw. The angle between the device and the current path,θ, is defined as the angle between a straight line connecting the two Hall plates and a line perpendicular to the current path.
两个霍尔板的位置和方向在不同的集成电路之间会有所不同。例如，ACS724使其霍尔板与ACS780中的霍尔板旋转90°，如图3所示。当使用CMR在任何Allegro电流传感器IC附近布线时，最好使θ角尽可能接近90°。
When it is not possible to keep θ close to 90°, the next best option is to keep the distance from the current path to the current sensor IC, d, as large as possible. Assuming that the current path is at the worst-case angle in relation to the IC, θ = 0° or 180°, the equation:
where H空间is the distance between the two Hall plates and Cf is the coupling factor of the IC. This coupling factor varies between the different ICs. The ACS780 has a coupling factor of 5 to 5.5 G/A, whereas other Allegro ICs can range from 10 to 15 G/A.
Error Estimation
Equation 1 assumes an infinitely long, infinitely thin wire. It does not take into account the width or thickness of the current-carrying conductor. Figure 4 shows the error calculated for a current-carrying conductor passing the ACS780 in the worst-case direction (θ = 0° or 180°). The error was calculated using the idealized equation as well as a more computationally intensive set of equations that take the width and thickness of the conductor into account. The plots show that the calculated error is higher using the idealized equation. Therefore, Equation 1 can be used as a quick, conservative estimation of the error.
Using the more accurate calculation method, the error was calculated for different widths of the current path as well as different angles between the device and the current path. For all angles and widths, 4 oz. copper was assumed to set the trace thickness. The plots show that the width of the current-carrying conductor does play a role in the error, but the biggest factors are the angle to the device, θ, and the distance from the device, d.
需要考虑的其他布局实践
When laying out a board that contains an Allegro current sensor IC with CMR, the direction and proximity of all current-carrying paths are important, but they are not the only factors to consider when optimizing IC performance. Other sources of stray fields that can contribute to system error include traces that connect to the IC’s integrated current conductor, as well as the position of nearby permanent magnets.
电路板与电流传感器IC的连接方式必须谨慎规划。可能影响性能的常见错误有：
- 电流路径到IP引脚的接近角
- Extending the current trace too far beneath the IC
接近角
One common mistake when using an Allegro current sensor IC is to bring the current in from an undesirable angle. Figure 6 shows an example of the approach of the current traces to the IC (in this case, the ACS724). In this figure, traces are shown for IP+ and IP–. The light green region is the desired area of approach for the current trace going to IP+. 该区域为0°至85°。这条规则同样适用于IP– trace.
该区域的限制是防止载流迹线产生任何杂散场，从而导致IC输出错误。当电流迹线连接到IP如果在这个区域之外，则必须按上面讨论的方式处理（来自附近电流路径的场）。
ENCROACHMENT UNDER THE IC
另一个common mistake is to route the current trace too far beyond the IP pins. Depending on the device, this can cause two different problems. In the case of devices in SOIC and similar packages, this can cause stray fields to be generated onto the IC, causing a decrease in performance. In the LR package, with its larger and exposed IP bus, routing too far beneath the package can change the current path through the IP bus, thus altering the performance of the device. This effect on the LR package will be covered in more detail in the next section.
对于杂散场的问题，当电流轨迹以一定角度进入IP总线时，问题会恶化。当这种情况发生时，电流实际上在零件下面流动，回到IP别针，然后通过IPpins. This altered current path can cause stray fields to be generated that reduce the accuracy of the IC. This can be prevented by not allowing the current trace to the IP插针侵入设备下方。
永磁体效应
当永磁体靠近电流传感器IC时，磁铁产生的杂散磁场也会影响IC的性能。一般来说，来自磁铁的杂散磁场会因磁铁而异。它将取决于磁铁的尺寸、材料、磁化方向和许多其他因素。如果电流传感器可以对齐，使霍尔板垂直于磁铁（如图8所示），这些杂散场的影响将最小化。
针对LR包的布局实践
ENCROACHMENT UNDER THE IC
In the LR package, the encroachment of the current-carrying trace under the device actually changes the path of the current flowing through the IP bus. This can cause a change in the coupling factor of the IP bus to the IC and can significantly reduce device performance.
利用ANSYS-Maxwell电磁分析软件，对电流产生的电流密度和磁场进行了数值模拟。在图9中，有两个不同模拟的结果。第一种情况是电流轨迹指向IP总线在所需的点终止。第二种情况是电流的踪迹远远地侵入IPbus. The red arrows in both simulations represent the areas of high current density. In the simulation with no excess overlap, the red areas, and hence the current density, are very different from the simulation with the excess overlap. It was also observed that the field on H1 was larger when there was no excess overlap. This can be observed by the darker shade of blue.
当重叠超过推荐值时，也会出现其他问题，例如，当前的接近角范围显著缩小。当电流的轨迹侵入到P总线太大，对接近角产生依赖，即接近角直接影响设备的耦合系数。避免这种情况的最佳方法是限制电流轨迹的重叠。
结论
亚博棋牌游戏快板微系统电流传感器集成电路有很多advantages. They have near-zero magnetic hysteresis as well as a very low power dissipation. One disadvantage that comes with the lack of a core is a susceptibility to stray fields. However, many ICs have the ability to reject common-mode magnetic fields.
The CMR techniques work best when the common-mode field on both Hall plates is equal. Several techniques were discussed to minimize the difference in the common-mode field on the two Hall plates—how to route external current paths and other optimal layout techniques. When current paths cannot be routed in the most favorable direction, the estimation of the error was also presented. Some layout techniques were also discussed that are specific to the LR package, as it has characteristics that must be considered for optimum performance.
Overall, the techniques and calculations discussed in this paper will help customers to optimize Allegro current sensor IC performance.